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semiconductor group 1 the hyb 5(3)14265bj(l) is the new generation dynamic ram organized as 262 144 words by 16-bit. the hyb 5(3)14265bj(l) utilizes the siemens 16m-cmos submicron silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. multiplexed address inputs permit the hyb 5(3)14265bj(l) to be packed in a standard plastic 400mil wide p-soj-40-3 package. this package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. the hyb314265bjl parts have a very low power sleep mode supported by self refresh. 256k x 16-bit edo-dynamic ram preliminary information ? 262 144 words by 16-bit organization ? 0 to 70 c operating temperature ? edo - hyper page mode ? performance: ? low power dissipation - active(max.): 120ma / 120ma / 105ma / 95 ma - standby : ttl inputs (max.) 2.0 ma - standby: cmos inputs (max.) 1.0 ma - standby (l-version) 200 m a -400 -40 -45 -50 t rc 69 69 79 89 ns t rac 40 40 45 50 ns t cac 10 10 12 13 ns t aa 20 20 22 25 ns t hpc 12,5 15 18 20 ns t hpc 80 66 55 50 mhz ? power supply: ? read, write, read-modify-write, cas -before ras refresh, ras only refresh, hidden refresh mode ? low power version (l) with self refresh and 250 m a self refresh current ? 2 cas / 1 we control ? all inputs and outputs ttl-compatible ? 512 refresh cycles / 16 ms 512 refresh cycles / 128 ms (l-version) ? plastic packages: p-soj-40-3 400 mil width hyb 514265bj-400 +5 v 5% hyb 514265bj-40 +5 v 10% hyb 514265bj-45 +5 v 10% hyb 514265bj-50 +5 v 10% hyb 314265bj(l)-45 +3.3 v 0.3 v hyb 314265bj(l)-50 +3.3 v 0.3 v 6.96 hyb 514265bj-400/40/-45/-50 hyb 314265bj(l)-45/-50
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 2 ordering information truth table pin names type ordering code package description 5 v versions: hyb 514265bj-400 q67100-3033 p-soj-40-3 5 v 40 ns 256 k x 16 edo-dram hyb 514265bj-40 q67100-3039 p-soj-40-3 5 v 40 ns 256 k x 16 edo-dram hyb 514265bj-45 q67100-3035 p-soj-40-3 5 v 45 ns 256 k x 16 edo-dram hyb 514265bj-50 q67100-3036 p-soj-40-3 5 v 50 ns 256 k x 16 edo-dram 3.3 v versions: hyb 314265bj-45 on request p-soj-40-3 3.3 v 45 ns 256 k x 16 edo- dram hyb 314265bj-50 on request p-soj-40-3 3.3 v 50 ns 256 k x 16 edo- dram hyb 314265bjl-45 on request p-soj-40-3 3.3 v low power 45 ns 256 k x 16 edo- dram hyb 314265bjl-50 on request p-soj-40-3 3.3 v low power 50 ns 256 k x 16 edo-dram ras lcas ucas we oe i/o1-i/o8 i/o9-i/o16 operation h l l l l l l l l h h l h l l h l l h h h l l h l l l h h h h h l l l h h h l l l h h h h high-z high-z dout high-z dout din don't care din high-z high-z high-z high-z dout dout don't care din din high-z standby refresh lower byte read upper byte read word read lower byte write upper byte write word write a0-a8 address inputs ras row address strobe ucas, lcas column address strobe we read/write input oe output enable i/o1 C i/o16 data input/output v cc power supply: + 5 v for hyb 514265, + 3.3 v for hyb 314265 v ss ground (0 v) n.c. no connection
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 3 pin configuration (top view) p-soj-40-3
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 4 block diagram
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 5 absolute maximum ratings operating temperature range ........................................................................................ 0 to + 70 c storage temperature range..................................................................................... C 55 to + 150 c input/output voltage for hyb 514265................................................ C 0.5 to min. ( v cc + 0.5, 7.0) v power supply voltage for hyb 514265 ........................................................................... C 1 to + 7 v input/output voltage for hyb 314265................................................ C 0.5 to min. ( v cc + 0.5, 4.6) v power supply voltage for hyb 314265 ..................................................................... C 0.5 to + 4.6 v data out current (short circuit) ................................................................................................ 50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics for hyb514265 t a = 0 to 70 c; v ss = 0 v; v cc = 5 v 10 % ( 5 % for -400 version) , t t = 2 ns parameter symbol limit values unit notes min. max. input high voltage v i h 2.4 v cc + 0.5 v 1 input low voltage v i l C 0.5 0.8 v 1 output high voltage ( i out = C 5.0 ma) v oh 2.4 C v 1 output low voltage ( i out = 4.2 ma) v ol C 0.4 v 1 input leakage current, any input (0 v < v i n < 7 v, all other inputs = 0 v) i i (l) C 10 10 m a 1 output leakage current (do is disabled, 0 v < v out < v cc ) i o(l) C 10 10 m a 1 average v cc supply current: -400 version -40 version -45 version -50 version i cc1 C 120 120 105 95 ma 2, 3, 4 standby v cc supply current ( ras = lcas = ucas = we = v ih ) i cc2 C 2 ma C average v cc supply current during ras-only refresh cycles: -400 version -40 version -45 version -50 version i cc3 C 120 120 105 95 ma 2, 4
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 6 dc characteristics for 314265 t a = 0 to 70 c; v ss = 0 v; v cc = 3.3 v 0.3 v, t t = 2 ns average v cc supply current during hyper page mode (edo) operation: -400 version -40 version -45 version -50 version i cc4 C 110 90 75 65 ma 2, 3, 4 standby v cc supply current ( ras = lcas = ucas = we = v cc C 0.2 v) i cc5 C1 ma 1 standby v cc supply current (l-version only) ( ras = lcas = ucas = we = v cc C 0.2 v) i cc5 C 200 m a 1 average v cc supply current during cas-before- ras refresh mode: -400 version -40 version -45 version -50 version i cc6 C 120 120 105 95 ma 2, 4 parameter symbol limit values unit test condition min. max. input high voltage v i h 2.0 v cc + 0.5 v 1 input low voltage v i l C 0.5 0.8 v 1 ttl output high voltage ( i out = C 2.0 ma) v oh 2.4 C v 1 ttl output low voltage ( i out = 2 ma) v ol C 0.4 v 1 cmos output high voltage ( i out = C 100 m a) v oh 2.4 C v 1 cmos output low voltage ( i out = 100 m a) v ol C 0.4 v 1 input leakage current, any input (0 v < v in < v cc + 0.3 v, all other inputs = 0 v) i i (l) C 10 10 m a 1 output leakage current (do is disabled, 0 v < v out < v cc + 0.3 v) i o(l) C 10 10 m a 1 average v cc supply current: -45 version -50 version i cc1 C 105 95 ma 2, 3, 4 standby v cc supply current ( ras = lcas = ucas = we = v ih ) i cc2 C 2 ma C parameter symbol limit values unit notes min. max.
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 7 capacitance t a = 0 to 70 c; f = 1 mhz average v cc supply current during ras-only refresh cycles: -45 version -50 version i cc3 C 105 95 ma 2, 4 average v cc supply current during hyper page mode (edo) operation: -45 version -50 version i cc4 C 75 65 ma 2, 3, 4 standby v cc supply current ( ras = lcas = ucas = we = v cc C 0.2 v) i cc5 C1ma 1 standby v cc supply current (l-version only) ( ras = lcas = ucas = we = v cc C 0.2 v) i cc5 C 200 m a 1 average v cc supply current during cas- before- ras refresh mode: -45 version -50 version i cc6 C 105 95 ma 2, 4 self refresh current (l-version only) cbr cycle with ras >trasss(min), cas held low; we = v cc C 0.2 v, addresses and din = v cc C 0.2 v or 0.2 v i cc7 C 250 m a parameter symbol limit values unit min. max. input capacitance (a0 to a8) c i 1 C5pf input capacitance ( ras, ucas, lcas, we, oe) c i 2 C7pf output capacitance (l/o1 to l/o16) c i o C7pf parameter symbol limit values unit test condition min. max.
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 8 ac characteristics 5) 6) t a = 0 to 70 c, t t = 2 ns parameter symbol limit values unit note -400 -40 min. max. min. max. common parameters random read or write cycle time t rc 69 C 69 C ns ras precharge time t rp 25 C 25 C ns ras pulse width t ras 40 10k 40 10k ns cas pulse width t cas 4.5 10k 6 10k ns cas precharge time t cp 4C5Cns row address setup time t asr 0C0Cns row address hold time t rah 5C5Cns column address setup time t asc 0C0Cns column address hold time t cah 5C5Cns ras to cas delaytime t rcd 9 30 9 30 ns ras to column address delay time t rad 7 20 7 20 ns ras hold time t rsh 6C6Cns cas hold time t csh 32 C 32 C ns cas to ras precharge time t crp 5C5Cns transition time(rise and fall) t t 1 50 1 50 ns 7 refresh period t ref 16 C 16 C ms read cycle access time from ras t rac C 40 C 40 ns 8, 9 access time from cas t cac C 10 C 10 ns 8, 9 access time from column address t aa C 17 C 20 ns 8,10 oe access time t oea C 10 C 10 ns column address to ras lead time t ral 20 C 20 C ns read command setup time t rcs 0C0Cns read command hold time t rch 0C0Cns 11 read command hold time ref. to ras t rrh 0C0Cns 11 cas to output inlow-z t clz 0C0Cns 8 output buffer turn-off delay from cas t off 0C010ns 12
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 9 output buffer turn-off delay from oe t oez 0 10 0 10 ns 12 data to oe low delay t dzo 0C0 ns 13 cas high to data delay t cdd 8C8Cns 14 oe high to data delay t odd 8C8Cns 14 data to cas low delay t dzc 0C0Cns 13 write cycle write command hold time t wch 5C5Cns write command pulse width t wp 5C5Cns write command setup time t wcs 0C0Cns 15 write command to ras lead time t rwl 10 C 10 C ns write command to cas lead time t cwl 10 C 10 C ns data setup time t ds 0C0Cns 16 data hold time t dh 5C5Cns 16 data to cas low delay t dzc 0C0Cns 13 read-modify-write cycle read-write cycle time t rwc 93 C 93 C ns ras to we delay time t rwd 52 C 52 C ns 15 cas to we delay time t cwd 22 C 22 C ns 15 column address to we delay time t awd 32 C 32 C ns 15 oe command hold time t oeh 5C5Cns hyper page mode (edo) cycle hyper page mode cycle time t hpc 12.5 C 15 C ns access time from cas precharge t cpa C 17 C 21 ns 7 output data hold time t coh 3C3Cns ras pulse width in hyper page mode t ras 40 200k 40 200k ns ras hold time from cas precharge t rhcp 17 C 21 C ns parameter symbol limit values unit note -400 -40 min. max. min. max.
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 10 hyper page mode (edo) read-modify-write cycle hyper page mode read/write cycle time t prwc 55 C 55 C ns cas precharge to we delay time t cpwd 35 C 35 C ns cas before ras refresh cycle cas setup time t csr 5C5Cns cas hold time t chr 5C5Cns ras to cas precharge time t rpc 5C5Cns write to ras precharge time t wrp 10 C 10 C ns write to ras hold time t wrh 10 C 10 C ns cas-before- ras counter test cycle cas precharge time t cpt 25 C 25 C ns parameter symbol limit values unit note -400 -40 min. max. min. max.
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 11 ac characteristics 5)6) 16e t a = 0 to 70 ?c, t t = 2 ns parameter symbol limit values unit note -45 -50 min. max. min. max. common parameters random read or write cycle time t rc 79 C 89 C ns ras precharge time t rp 30 C 35 C ns ras pulse width t ras 45 10k 50 10k ns cas pulse width t cas 7 10k 8 10k ns cas precharge time t cp 7C8Cns row address setup time t asr 0C0Cns row address hold time t rah 7C8Cns column address setup time t asc 0C0Cns column address hold time t cah 7C8Cns ras to cas delay time t rcd 11 33 12 37 ns ras to column address delay t rad 9 231025ns ras hold time t rsh 12 13 C ns cas hold time t csh 36 40 C ns cas to ras precharge time t crp 5C5Cns transition time (rise and fall) t t 1 50 1 50 ns 7 refresh period t ref C 16 C 16 ms refresh period (l-version only) t ref C 128 C 128 ms read cycle access time from ras t rac C 45 C 50 ns 8, 9 access time from cas t cac C 12 C 13 ns 8, 9 access time from column address t aa C 22 C 25 ns 8,10 oe access time t oea C 12 C 13 ns column address to ras lead time t ral 23 C 25 C ns read command setup time t rcs 0C0Cns read command hold time t rch 0C0Cns11 read command hold time referenced to ras t rrh 0C0Cns11 cas to output in low-z t clz 0C0Cns8
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 12 output buffer turn-off delay t off 0 12 0 13 ns 12 output turn-off delay from oe t oez 0 12 0 13 ns 12 data to cas low delay t dzc 0C0Cns13 data to oe low delay t dzo 0C0Cns13 cas high to data delay t cdd 10 C 10 C ns 14 oe high to data delay t odd 10 C 10 C ns 14 write cycle write command hold time t wch 7C8Cns write command pulse width t wp 7C8Cns write command setup time t wcs 0C0Cns15 write command to ras lead time t rwl 12 C 13 C ns write command to cas lead time t cwl 12 C 13 C ns data setup time t ds 0C0Cns16 data hold time t dh 7C8Cns16 read-modify-write cycle read-write cycle time t rwc 107 C 118 C ns ras to we delay time t rwd 59 C 64 C ns 15 cas to we delay time t cwd 26 C 27 C ns 15 column address to we delay time t awd 36 C 39 C ns 15 oe command hold time t oeh 7C10Cns hyper page mode (edo) cycle hyper page mode (edo) cycle time t hpc 18 C 20 C ns access time from cas precharge t cpa C 25 C 27 ns 7 output data hold time t coh 5C5Cns ras pulse width in edo mode t ras 45 200k 50 200k ns cas precharge to ras delay t rhpc 25 C 27 C ns ac characteristics (contd) 5)6) 16e t a = 0 to 70 ?c, t t = 2 ns parameter symbol limit values unit note -45 -50 min. max. min. max.
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 13 notes: 1) all voltages are referenced to v ss . 2) i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 3) i cc1 and i cc4 depend on output loading. specified values are obtained with the output open. 4) address can be changed once or less while ras = v il . in case of i cc4 it can be changed once or less during a hyper page mode (edo) cycle 5) an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using the internal refresh counter, a minimum of 8 cas-before- ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume t t = 2 ns. hyper page mode (edo) read-modify-write cycle hyper page mode (edo) read-write cycle time t prwc 51 C 58 C ns cas precharge to we t cpwd 41 C 41 C ns cas-before- ras refresh cycle cas setup time t csr 5C10Cns cas hold time t chr 10 C 10 C ns ras to cas precharge time t rpc 5C5Cns write to ras precharge time t wrp 10 C 10 C ns write hold time referenced to ras t wrh 10 C 10 C ns cas-before- ras counter test cycle cas precharge time t cpt 30 C 35 C ns self refresh cycle (l-version) ras pulse width t rass 100k C 100k C ns 17 ras precharge t rps 110 C 95 C ns 17 cas hold time t chs C 50 C C 50 C ns 17 ac characteristics (contd) 5)6) 16e t a = 0 to 70 ?c, t t = 2 ns parameter symbol limit values unit note -45 -50 min. max. min. max.
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 14 7) v i h (min.) and v i l (max.) are reference levels for measuring timing of input signals. transition times are also measured between v i h and v i l . 8) measured with the specified current load and 50 pf at v ol = 0.8 v and v oh = 2.0 v. access time is determined by the latter of t rac , t cac , t aa , t cpa , t oea . t cac is measured from tristate . 9) operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 10) operation within the t rad (max. ) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 11) either t rch or t rrh must be satisfied for a read cycle. 12) t off (max.) , t oez (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. t off is referenced from the rising edge of ras or cas, whichever occurs last. 13) either t dzc or t dzo must be satisfied. 14) either t cdd or t odd must be satisfied. 15) t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs > t wcs (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if t rwd > t rwd (min.) , t cwd > t cwd (min.) and t awd > t awd (min.) , the cycle is a read-write cycle and i/o will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of i/o (at access time) is indeterminate. 16) these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read-write cycles. 17)when using self refresh mode, the following refresh operations must be performed to ensure proper dram operation: if row addresses are being refreshed on an evenly distributed manner over the refresh interval using cbr refresh cycles, then only one cbr cycle must be performed immediately after exit from self refresh. if row addresses are being refreshed in any other manner (ror - distributed/burst; or cbr-burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from self refresh. 50 pf i/o z=50 ohm + 1.5 v 50 ohm fig.2
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 15 read cycle
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 16 write cycle (early write)
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 17 write cycle ( oe controlled write)
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 18 read-write (read-modify-write) cycle
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 19 hyper page mode (edo) read cycle
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 20 hyper page mode (edo) early write cycle
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 21 hyper page mode (edo) late write and read-modify-write cycles
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 22 ras-only refresh cycle
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 23 cas-before- ras refresh cycle
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 24 cas before ras self refresh cycle
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 25 hidden refresh cycle (read)
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 26 hidden refresh cycle (early write)
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 27 cas-before- ras refresh counter test cycle
hyb 5(3)14265bj(l)-400/-40/-45/-50 256k x 16 edo-dram semiconductor group 28 package outlines p-soj-40-3 (small outline j-leaded package) gpj09018 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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